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<meta name="description" content="关键词： setup hold recovery removal width period 指定路径延迟，目的是让仿真的时序更加接近实际数字电路的时序。利用时序约束对数字设计进行时序仿真，检查设计是否存在违反（violation）时序约束的地方，并加以修改，也是数字设计中不可或缺的过程。 Verilog 提供了一些系统任务，用于时序检查。这些系统任务只能在 specify 块中调用。下面就介绍 6 种常用的用于时序检查的系统任务：$se..">
		
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				<h2>3.4 Verilog 时序检查</h2>				<h3><em>分类</em> <a href="../w3cnote_genre/verilog2" title="Verilog 教程高级篇" >Verilog 教程高级篇</a> </h3>
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					<h3>关键词： setup hold recovery removal width period</h3>
<p>指定路径延迟，目的是让仿真的时序更加接近实际数字电路的时序。利用时序约束对数字设计进行时序仿真，检查设计是否存在违反（violation）时序约束的地方，并加以修改，也是数字设计中不可或缺的过程。</p><p>
Verilog 提供了一些系统任务，用于时序检查。这些系统任务只能在 specify 块中调用。下面就介绍 6 种常用的用于时序检查的系统任务：$setup, $hold, $recovery, $removal, $width 与 $period。</p>

<h3>$setup, $hold</h3><p>
系统任务 $setup 用来检查设计中元件的建立时间约束条件，$hold 用来检查保持时间约束条件。其用法格式如下：</p>
<pre>
$setup(data_event, ref_event, setup_limit);</pre>
<ul><li>
data_event: 被检查的信号，判断它是否违反约束</li><li>
ref_event: 用于检查的参考信号，一般为时钟信号的跳变沿</li><li>
setup_limit: 设置的最小建立时间</li></ul><p>
如果 <strong>T( ref_event - data_event) &lt; setup_limit</strong>， 则会打印存在 <strong>violation</strong> 的报告。</p>

<pre>$hold(ref_event, data_event, hold_limit);</pre><ul><li>

data_event: 被检查的信号，判断它是否违反约束</li><li>
ref_event: 用于检查的参考信号，一般为时钟信号的跳变沿</li><li>
hold_limit: 设置的最小保持时间</li></ul>
<p>如果 <strong>T( data_event - ref_event ) &lt; hold_limit</strong>， 则会打印存在 <strong>violation</strong> 的报告。</p>

<p><strong>注意:</strong> $setup 和 $hold 输入端口的位置是不同的。</p>
<p>Verilog 提供了同时检查建立时间和保持时间的系统任务：</p><pre>
$setuphold (ref_event, data_event, setup_limit, hold_limit);</pre>
<p>
下面完成一个数乘以 15 的操作，来说明 $setup 和 $hold 的用法。</p><p>
Verilog 中，一个变量乘以常数一般用移位相加的方法来完成，例如对变量 num 乘以 15 的操作可以表示为：</p>
<pre>num x 15 = (num &lt;&lt; 3) + (num &lt;&lt; 2) + (num &lt;&lt; 1) + num</pre><p>
此操作需要 3 个加法器。下面对加法器进行建模，并指定路径延迟。</p><p>
全加器功能描述可参考<a href="../w3cnote/verilog-assign.html" rel="noopener" target="_blank">《Verilog 教程》的 3.1 节内容</a>。</p>
<div class="example"><h2 class="example">实例</h2> <div class="example_code">
<span style="color: #00008B; font-style: italic;">//单 bit 全加器，指定路径延迟</span><br />
<span style="color: #A52A2A; font-weight: bold;">module</span> full_adder1<span style="color: #9F79EE;">&#40;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">input</span> &nbsp; Ai<span style="color: #5D478B;">,</span> Bi<span style="color: #5D478B;">,</span> Ci<span style="color: #5D478B;">,</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">output</span> &nbsp;So<span style="color: #5D478B;">,</span> Co<span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">;</span><br />
<br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">assign</span> So <span style="color: #5D478B;">=</span> Ai <span style="color: #5D478B;">^</span> Bi <span style="color: #5D478B;">^</span> Ci <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">assign</span> Co <span style="color: #5D478B;">=</span> <span style="color: #9F79EE;">&#40;</span>Ai <span style="color: #5D478B;">&amp;</span> Bi<span style="color: #9F79EE;">&#41;</span> <span style="color: #5D478B;">|</span> <span style="color: #9F79EE;">&#40;</span>Ci <span style="color: #5D478B;">&amp;</span> <span style="color: #9F79EE;">&#40;</span>Ai <span style="color: #5D478B;">|</span> Bi<span style="color: #9F79EE;">&#41;</span><span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">;</span><br />
<br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">specify</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #9F79EE;">&#40;</span>Ai<span style="color: #5D478B;">,</span> Bi<span style="color: #5D478B;">,</span> Ci <span style="color: #5D478B;">*&gt;</span> So<span style="color: #9F79EE;">&#41;</span> <span style="color: #5D478B;">=</span> <span style="color: #ff0055;">1.1</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #9F79EE;">&#40;</span>Ai<span style="color: #5D478B;">,</span> Bi &nbsp; &nbsp; <span style="color: #5D478B;">*&gt;</span> Co<span style="color: #9F79EE;">&#41;</span> <span style="color: #5D478B;">=</span> <span style="color: #ff0055;">1.3</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #9F79EE;">&#40;</span>Ci &nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #5D478B;">=&gt;</span> Co<span style="color: #9F79EE;">&#41;</span> <span style="color: #5D478B;">=</span> <span style="color: #ff0055;">1.2</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">endspecify</span><br />
<span style="color: #A52A2A; font-weight: bold;">endmodule</span><br />
<br />
<span style="color: #00008B; font-style: italic;">//8bit 位宽加法器例化</span><br />
<span style="color: #A52A2A; font-weight: bold;">module</span> full_adder8<span style="color: #9F79EE;">&#40;</span><br />
&nbsp; &nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">input</span> <span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">7</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span> &nbsp; a <span style="color: #5D478B;">,</span> &nbsp; <span style="color: #00008B; font-style: italic;">//adder1</span><br />
&nbsp; &nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">input</span> <span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">7</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span> &nbsp; b <span style="color: #5D478B;">,</span> &nbsp; <span style="color: #00008B; font-style: italic;">//adder2</span><br />
&nbsp; &nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">input</span> &nbsp; &nbsp; &nbsp; &nbsp; c <span style="color: #5D478B;">,</span> &nbsp; <span style="color: #00008B; font-style: italic;">//input carry bit</span><br />
&nbsp; &nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">output</span> <span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">7</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span> &nbsp;so <span style="color: #5D478B;">,</span> &nbsp;<span style="color: #00008B; font-style: italic;">//adding result</span><br />
&nbsp; &nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">output</span> &nbsp; &nbsp; &nbsp; &nbsp;co &nbsp; &nbsp;<span style="color: #00008B; font-style: italic;">//output carry bit</span><br />
&nbsp; &nbsp; &nbsp;<span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">;</span><br />
<br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">wire</span> <span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">7</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span> &nbsp; &nbsp; &nbsp;co_temp <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;full_adder1 &nbsp;u_adder0<span style="color: #9F79EE;">&#40;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;.Ai &nbsp; &nbsp; <span style="color: #9F79EE;">&#40;</span>a<span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span><span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">,</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;.Bi &nbsp; &nbsp; <span style="color: #9F79EE;">&#40;</span>b<span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span><span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">,</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;.Ci &nbsp; &nbsp; <span style="color: #9F79EE;">&#40;</span>c<span style="color: #5D478B;">==</span><span style="color: #ff0055;">1'b1</span> <span style="color: #5D478B;">?</span> <span style="color: #ff0055;">1'b1</span> <span style="color: #5D478B;">:</span> <span style="color: #ff0055;">1'b0</span><span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">,</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;.So &nbsp; &nbsp; <span style="color: #9F79EE;">&#40;</span>so<span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span><span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">,</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;.Co &nbsp; &nbsp; <span style="color: #9F79EE;">&#40;</span>co_temp<span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span><span style="color: #9F79EE;">&#41;</span><span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">;</span><br />
<br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">genvar</span> &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;i <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">generate</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">for</span><span style="color: #9F79EE;">&#40;</span>i<span style="color: #5D478B;">=</span><span style="color: #ff0055;">1</span><span style="color: #5D478B;">;</span> i<span style="color: #5D478B;">&lt;=</span><span style="color: #ff0055;">7</span><span style="color: #5D478B;">;</span> i<span style="color: #5D478B;">=</span>i<span style="color: #5D478B;">+</span><span style="color: #ff0055;">1</span><span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><span style="color: #5D478B;">:</span> adder_gen<br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp;full_adder1 &nbsp;u_adder<span style="color: #9F79EE;">&#40;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; .Ai &nbsp; &nbsp; <span style="color: #9F79EE;">&#40;</span>a<span style="color: #9F79EE;">&#91;</span>i<span style="color: #9F79EE;">&#93;</span><span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">,</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; .Bi &nbsp; &nbsp; <span style="color: #9F79EE;">&#40;</span>b<span style="color: #9F79EE;">&#91;</span>i<span style="color: #9F79EE;">&#93;</span><span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">,</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; .Ci &nbsp; &nbsp; <span style="color: #9F79EE;">&#40;</span>co_temp<span style="color: #9F79EE;">&#91;</span>i<span style="color: #5D478B;">-</span><span style="color: #ff0055;">1</span><span style="color: #9F79EE;">&#93;</span><span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">,</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; .So &nbsp; &nbsp; <span style="color: #9F79EE;">&#40;</span>so<span style="color: #9F79EE;">&#91;</span>i<span style="color: #9F79EE;">&#93;</span><span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">,</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; .Co &nbsp; &nbsp; <span style="color: #9F79EE;">&#40;</span>co_temp<span style="color: #9F79EE;">&#91;</span>i<span style="color: #9F79EE;">&#93;</span><span style="color: #9F79EE;">&#41;</span><span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">endgenerate</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">assign</span> co &nbsp; &nbsp;<span style="color: #5D478B;">=</span> co_temp<span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">7</span><span style="color: #9F79EE;">&#93;</span> <span style="color: #5D478B;">;</span><br />
<span style="color: #A52A2A; font-weight: bold;">endmodule</span><br />
</div></div>
<p>8bit 位宽的触发器描述如下。触发器中指定路径延迟，并加入建立时间和保持时间的时序检查。</p><p>
建立时间设置为 2ns，保持时间设置为 3ns。</p>
<div class="example"><h2 class="example">实例</h2> <div class="example_code">
<span style="color: #A52A2A; font-weight: bold;">module</span> D8<span style="color: #9F79EE;">&#40;</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">input</span> &nbsp; &nbsp; &nbsp; <span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">7</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span> &nbsp; d <span style="color: #5D478B;">,</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">input</span> &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; clk <span style="color: #5D478B;">,</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">output</span> <span style="color: #A52A2A; font-weight: bold;">reg</span> <span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">7</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span> &nbsp; &nbsp;q<span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">;</span><br />
<br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">always</span> <span style="color: #5D478B;">@</span><span style="color: #9F79EE;">&#40;</span><span style="color: #A52A2A; font-weight: bold;">posedge</span> clk<span style="color: #9F79EE;">&#41;</span><br />
&nbsp; &nbsp; &nbsp;q <span style="color: #5D478B;">&lt;=</span> d <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">specify</span><br />
&nbsp; &nbsp; &nbsp; $setup<span style="color: #9F79EE;">&#40;</span>d<span style="color: #5D478B;">,</span> <span style="color: #A52A2A; font-weight: bold;">posedge</span> clk<span style="color: #5D478B;">,</span> <span style="color: #ff0055;">2</span><span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; $hold<span style="color: #9F79EE;">&#40;</span><span style="color: #A52A2A; font-weight: bold;">posedge</span> clk<span style="color: #5D478B;">,</span> d<span style="color: #5D478B;">,</span> <span style="color: #ff0055;">3</span><span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #9F79EE;">&#40;</span>d<span style="color: #5D478B;">,</span>clk <span style="color: #5D478B;">*&gt;</span> q<span style="color: #9F79EE;">&#41;</span> <span style="color: #5D478B;">=</span> <span style="color: #ff0055;">0.3</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">endspecify</span><br />
<span style="color: #A52A2A; font-weight: bold;">endmodule</span><br />
</div></div><p>
在 testbench 里完成乘以 15 的操作，并在一个周期内输出给下一级寄存器。</p>
<div class="example"><h2 class="example">实例</h2> <div class="example_code">
<span style="color: #008800;">`timescale</span> <span style="color: #ff0055;">1ns</span><span style="color: #5D478B;">/</span><span style="color: #ff0055;">1ns</span><br />
<span style="color: #A52A2A; font-weight: bold;">module</span> test <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">reg</span> &nbsp;<span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">3</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span> &nbsp; a <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">reg</span> &nbsp;<span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">3</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span> &nbsp; b <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">wire</span> <span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">3</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span> &nbsp; so <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">wire</span> &nbsp; &nbsp; &nbsp; &nbsp; co <span style="color: #5D478B;">;</span><br />
<br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">parameter</span> &nbsp; &nbsp;CYCLE_10NS <span style="color: #5D478B;">=</span> <span style="color: #ff0055;">10ns</span><span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">reg</span> &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;clk <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">initial</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; clk <span style="color: #5D478B;">=</span> <span style="color: #ff0055;">0</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #5D478B;">#</span> <span style="color: #ff0055;">111</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">forever</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #5D478B;">#</span><span style="color: #9F79EE;">&#40;</span>CYCLE_10NS<span style="color: #5D478B;">/</span><span style="color: #ff0055;">2</span><span style="color: #9F79EE;">&#41;</span> clk <span style="color: #5D478B;">=</span> <span style="color: #5D478B;">~</span>clk <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">end</span><br />
<br />
&nbsp; &nbsp;<span style="color: #00008B; font-style: italic;">//需要乘以 15 的数</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">reg</span> <span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">7</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span> &nbsp; &nbsp;num <span style="color: #5D478B;">=</span> <span style="color: #ff0055;">0</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">always</span> <span style="color: #5D478B;">@</span><span style="color: #9F79EE;">&#40;</span><span style="color: #A52A2A; font-weight: bold;">posedge</span> clk<span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; num<span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">3</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span> <span style="color: #5D478B;">&lt;=</span> num<span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">3</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span> <span style="color: #5D478B;">+</span> <span style="color: #ff0055;">1</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">end</span><br />
<br />
&nbsp; &nbsp;<span style="color: #00008B; font-style: italic;">// num * 8 + num * 4</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">wire</span> <span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">7</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span> &nbsp; &nbsp;adder1 <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;full_adder8 &nbsp;u1_adder8<span style="color: #9F79EE;">&#40;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;.a &nbsp; &nbsp; &nbsp;<span style="color: #9F79EE;">&#40;</span>num<span style="color: #5D478B;">&lt;&lt;</span><span style="color: #ff0055;">2</span><span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">,</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;.b &nbsp; &nbsp; &nbsp;<span style="color: #9F79EE;">&#40;</span>num<span style="color: #5D478B;">&lt;&lt;</span><span style="color: #ff0055;">3</span><span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">,</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;.c &nbsp; &nbsp; &nbsp;<span style="color: #9F79EE;">&#40;</span><span style="color: #ff0055;">1'b0</span><span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">,</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;.so &nbsp; &nbsp; <span style="color: #9F79EE;">&#40;</span>adder1<span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">,</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;.co &nbsp; &nbsp; <span style="color: #9F79EE;">&#40;</span><span style="color: #9F79EE;">&#41;</span><span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #00008B; font-style: italic;">//num * 2 + num</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">wire</span> <span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">7</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span> &nbsp; &nbsp;adder2 <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;full_adder8 &nbsp;u2_adder8<span style="color: #9F79EE;">&#40;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;.a &nbsp; &nbsp; &nbsp;<span style="color: #9F79EE;">&#40;</span>num<span style="color: #5D478B;">&lt;&lt;</span><span style="color: #ff0055;">1</span><span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">,</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;.b &nbsp; &nbsp; &nbsp;<span style="color: #9F79EE;">&#40;</span>num<span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">,</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;.c &nbsp; &nbsp; &nbsp;<span style="color: #9F79EE;">&#40;</span><span style="color: #ff0055;">1'b0</span><span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">,</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;.so &nbsp; &nbsp; <span style="color: #9F79EE;">&#40;</span>adder2<span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">,</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;.co &nbsp; &nbsp; <span style="color: #9F79EE;">&#40;</span><span style="color: #9F79EE;">&#41;</span><span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #00008B; font-style: italic;">//num x 15</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">wire</span> <span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">7</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span> &nbsp; &nbsp;adder3 <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;full_adder8 &nbsp;u3_adder8<span style="color: #9F79EE;">&#40;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;.a &nbsp; &nbsp; &nbsp;<span style="color: #9F79EE;">&#40;</span>adder1<span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">,</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;.b &nbsp; &nbsp; &nbsp;<span style="color: #9F79EE;">&#40;</span>adder2<span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">,</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;.c &nbsp; &nbsp; &nbsp;<span style="color: #9F79EE;">&#40;</span><span style="color: #ff0055;">1'b0</span><span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">,</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;.so &nbsp; &nbsp; <span style="color: #9F79EE;">&#40;</span>adder3<span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">,</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;.co &nbsp; &nbsp; <span style="color: #9F79EE;">&#40;</span><span style="color: #9F79EE;">&#41;</span><span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<br />
&nbsp; &nbsp;<span style="color: #00008B; font-style: italic;">//store the result</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">wire</span> <span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">7</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span> &nbsp; &nbsp;res_mul15 <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;D8 &nbsp; data_store<span style="color: #9F79EE;">&#40;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;.d &nbsp; &nbsp; &nbsp; <span style="color: #9F79EE;">&#40;</span>adder3<span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">,</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;.clk &nbsp; &nbsp; <span style="color: #9F79EE;">&#40;</span>clk<span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">,</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;.q &nbsp; &nbsp; &nbsp; <span style="color: #9F79EE;">&#40;</span>res_mul15<span style="color: #9F79EE;">&#41;</span><span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">;</span><br />
<br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">initial</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">forever</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp;<span style="color: #5D478B;">#</span><span style="color: #ff0055;">100</span><span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">if</span> <span style="color: #9F79EE;">&#40;</span><span style="color: #9932CC;">$time</span> <span style="color: #5D478B;">&gt;=</span> <span style="color: #ff0055;">1000</span><span style="color: #9F79EE;">&#41;</span> &nbsp;<span style="color: #9932CC;">$finish</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">end</span><br />
<span style="color: #A52A2A; font-weight: bold;">endmodule</span> <span style="color: #00008B; font-style: italic;">// test</span><br />
</div></div><p>
仿真报告中则出现了带有 setup/hold violation 的打印信息，部分截图如下。</p>
<p><img decoding="async" src="https://www.runoob.com/wp-content/uploads/2021/05/v-timing-check-1.png"></p>
<p>截取出现 violation 时间的波形图，如下所示。</p><p><img decoding="async" src="https://www.runoob.com/wp-content/uploads/2021/05/v-timing-check-2.png"></p>
<p>分析如下：</p><ul><li>
(1) 建立时间和保持时间均出现了 violation，虽然仿真中变量 num 乘以 15 以后延迟一个时钟周期的输出结果是正确的，但实际电路是很危险的。</li><li>
(2) 波形中信号的建立时间 166-164.4 = 1.6 ns，小于设置的 2ns，所以会报告 violation。</li><li>
(3) 波形中信号的保持时间 168.2-166 = 2.2 ns，小于设置的 3ns，所以会报告 violation。</li><li>
(4) 图中红色部分是信号 d 变化的中间过程，因为信号各 bit 延迟不同，所以中间可能会出现多个不同的结果。</li></ul>

<h3>时序优化</h3><p>
保持时间的时序优化，在 RTL 层级描述上一般不好控制，这属于后端设计工程师的工作范畴，这里不做讨论。</p><p>
本次主要简单探讨建立时间不满足约束条件时的优化问题。由上一节《3.3 建立时间和保持时间》中可知建立时间约束表达式为：</p>
<pre>Tcq + Tcomb + Tsu &lt;= Tclk + Tskew （1）</pre><ul><li>
Tcq: 寄存器 clock 端到 Q 端的延迟；</li><li>
Tcomb： data path 中的组合逻辑延迟；</li><li>
Tsu: 建立时间；</li><li>
Tclk: 时钟周期；</li><li>
Tskew: 时钟偏移。</li></ul>
<p>优化此不等式可从以下几个方面考虑：</p><ul><li>
(1) 选取时序较好的工艺原件，其 Tcq 和 Tsu 值越小越好；</li><li>
(2) 优化组合逻辑，使组合逻辑延迟 Tcomb 越小越好；</li><li>
(3) 降低工作时钟频率，增大工作时钟周期 Tclk；</li><li>
(4) 增加时钟偏移 Tskew，但时钟偏移过大又会造成其他问题，例如保持时间可能不满足，功能逻辑错误等。
</li></ul><p>
从 RTL 层次进行时序优化时，只能考虑方法（2）（3）。</p><p>
例如，将上述仿真中的工作时钟周期由 10ns 改为 20ns，则不会出现 setup violation。</p><p>
或者，调整逻辑，一个周期内完成 3 次加法运算，改为分散到两个周期内完成，中间增加一级寄存器进行缓冲，来减少时序上的压力。同时，变量 num 的变化周期也应该变为原来的 2 倍时长。</p>
<p>testbench 修改如下：</p>
<div class="example"><h2 class="example">实例</h2> <div class="example_code">
<span style="color: #008800;">`timescale</span> <span style="color: #ff0055;">1ns</span><span style="color: #5D478B;">/</span><span style="color: #ff0055;">1ns</span><br />
<span style="color: #008800;">`define</span> LOGIC_BUF<br />
<span style="color: #A52A2A; font-weight: bold;">module</span> test <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">parameter</span> &nbsp; &nbsp;CYCLE_10NS <span style="color: #5D478B;">=</span> <span style="color: #ff0055;">10ns</span><span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">reg</span> &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;clk <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">initial</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; clk <span style="color: #5D478B;">=</span> <span style="color: #ff0055;">0</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #5D478B;">#</span> <span style="color: #ff0055;">111</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">forever</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #5D478B;">#</span><span style="color: #9F79EE;">&#40;</span>CYCLE_10NS<span style="color: #5D478B;">/</span><span style="color: #ff0055;">2</span><span style="color: #9F79EE;">&#41;</span> clk <span style="color: #5D478B;">=</span> <span style="color: #5D478B;">~</span>clk <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">end</span><br />
<br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">reg</span> &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;slow_flag <span style="color: #5D478B;">=</span> <span style="color: #ff0055;">0</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">always</span> <span style="color: #5D478B;">@</span><span style="color: #9F79EE;">&#40;</span><span style="color: #A52A2A; font-weight: bold;">posedge</span> clk<span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
<span style="color: #008800;">`ifdef</span> LOGIC_BUF<br />
&nbsp; &nbsp; &nbsp; slow_flag <span style="color: #5D478B;">&lt;=</span> <span style="color: #5D478B;">~</span>slow_flag <span style="color: #5D478B;">;</span><br />
`<span style="color: #A52A2A; font-weight: bold;">else</span><br />
&nbsp; &nbsp; &nbsp; slow_flag <span style="color: #5D478B;">&lt;=</span> <span style="color: #ff0055;">1'b1</span> <span style="color: #5D478B;">;</span><br />
<span style="color: #008800;">`endif</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">end</span><br />
<br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">reg</span> &nbsp;<span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">7</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span> &nbsp; &nbsp;num <span style="color: #5D478B;">=</span> <span style="color: #ff0055;">0</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">always</span> <span style="color: #5D478B;">@</span><span style="color: #9F79EE;">&#40;</span><span style="color: #A52A2A; font-weight: bold;">posedge</span> clk<span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">if</span><span style="color: #9F79EE;">&#40;</span>slow_flag<span style="color: #9F79EE;">&#41;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; num<span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">3</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span> <span style="color: #5D478B;">&lt;=</span> num<span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">3</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span> <span style="color: #5D478B;">+</span> <span style="color: #ff0055;">1</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">end</span><br />
<br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">wire</span> <span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">7</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span> &nbsp; &nbsp;adder1 <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;full_adder8 &nbsp;u1_adder8<span style="color: #9F79EE;">&#40;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;.a &nbsp; &nbsp; &nbsp;<span style="color: #9F79EE;">&#40;</span>num<span style="color: #5D478B;">&lt;&lt;</span><span style="color: #ff0055;">2</span><span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">,</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;.b &nbsp; &nbsp; &nbsp;<span style="color: #9F79EE;">&#40;</span>num<span style="color: #5D478B;">&lt;&lt;</span><span style="color: #ff0055;">3</span><span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">,</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;.c &nbsp; &nbsp; &nbsp;<span style="color: #9F79EE;">&#40;</span><span style="color: #ff0055;">1'b0</span><span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">,</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;.so &nbsp; &nbsp; <span style="color: #9F79EE;">&#40;</span>adder1<span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">,</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;.co &nbsp; &nbsp; <span style="color: #9F79EE;">&#40;</span><span style="color: #9F79EE;">&#41;</span><span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">;</span><br />
<br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">wire</span> <span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">7</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span> &nbsp; &nbsp;adder2 <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;full_adder8 &nbsp;u2_adder8<span style="color: #9F79EE;">&#40;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;.a &nbsp; &nbsp; &nbsp;<span style="color: #9F79EE;">&#40;</span>num<span style="color: #5D478B;">&lt;&lt;</span><span style="color: #ff0055;">1</span><span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">,</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;.b &nbsp; &nbsp; &nbsp;<span style="color: #9F79EE;">&#40;</span>num<span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">,</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;.c &nbsp; &nbsp; &nbsp;<span style="color: #9F79EE;">&#40;</span><span style="color: #ff0055;">1'b0</span><span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">,</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;.so &nbsp; &nbsp; <span style="color: #9F79EE;">&#40;</span>adder2<span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">,</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;.co &nbsp; &nbsp; <span style="color: #9F79EE;">&#40;</span><span style="color: #9F79EE;">&#41;</span><span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">;</span><br />
<br />
&nbsp; &nbsp;<span style="color: #00008B; font-style: italic;">//====== for better time=========</span><br />
&nbsp; &nbsp;<span style="color: #00008B; font-style: italic;">//adding buffer</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">wire</span> <span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">7</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span> &nbsp; &nbsp;adder1_r<span style="color: #5D478B;">,</span> adder2_r <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;D8 &nbsp; adder1_buf<span style="color: #9F79EE;">&#40;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;.d &nbsp; &nbsp; &nbsp; <span style="color: #9F79EE;">&#40;</span>adder1<span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">,</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;.clk &nbsp; &nbsp; <span style="color: #9F79EE;">&#40;</span>clk<span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">,</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;.q &nbsp; &nbsp; &nbsp; <span style="color: #9F79EE;">&#40;</span>adder1_r<span style="color: #9F79EE;">&#41;</span><span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;D8 &nbsp; adder2_buf<span style="color: #9F79EE;">&#40;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;.d &nbsp; &nbsp; &nbsp; <span style="color: #9F79EE;">&#40;</span>adder2<span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">,</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;.clk &nbsp; &nbsp; <span style="color: #9F79EE;">&#40;</span>clk<span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">,</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;.q &nbsp; &nbsp; &nbsp; <span style="color: #9F79EE;">&#40;</span>adder2_r<span style="color: #9F79EE;">&#41;</span><span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">;</span><br />
<br />
<span style="color: #008800;">`ifdef</span> LOGIC_BUF<br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">wire</span> <span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">7</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span> &nbsp; &nbsp; &nbsp; &nbsp; adder1_t &nbsp; &nbsp; &nbsp; <span style="color: #5D478B;">=</span> adder1_r <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">wire</span> <span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">7</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span> &nbsp; &nbsp; &nbsp; &nbsp; adder2_t &nbsp; &nbsp; &nbsp; <span style="color: #5D478B;">=</span> adder2_r <span style="color: #5D478B;">;</span><br />
`<span style="color: #A52A2A; font-weight: bold;">else</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">wire</span> <span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">7</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span> &nbsp; &nbsp; &nbsp; &nbsp; adder1_t &nbsp; &nbsp; &nbsp; <span style="color: #5D478B;">=</span> adder1 <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">wire</span> <span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">7</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span> &nbsp; &nbsp; &nbsp; &nbsp; adder2_t &nbsp; &nbsp; &nbsp; <span style="color: #5D478B;">=</span> adder2 <span style="color: #5D478B;">;</span><br />
<span style="color: #008800;">`endif</span><br />
<br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">wire</span> <span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">7</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span> &nbsp; &nbsp;adder3 <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;full_adder8 &nbsp;u3_adder8<span style="color: #9F79EE;">&#40;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;.a &nbsp; &nbsp; &nbsp;<span style="color: #9F79EE;">&#40;</span>adder1_t<span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">,</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;.b &nbsp; &nbsp; &nbsp;<span style="color: #9F79EE;">&#40;</span>adder2_t<span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">,</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;.c &nbsp; &nbsp; &nbsp;<span style="color: #9F79EE;">&#40;</span><span style="color: #ff0055;">1'b0</span><span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">,</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;.so &nbsp; &nbsp; <span style="color: #9F79EE;">&#40;</span>adder3<span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">,</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;.co &nbsp; &nbsp; <span style="color: #9F79EE;">&#40;</span><span style="color: #9F79EE;">&#41;</span><span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">;</span><br />
<br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">wire</span> <span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">7</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span> &nbsp; &nbsp;res_mul15 <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;D8 &nbsp; data_store<span style="color: #9F79EE;">&#40;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;.d &nbsp; &nbsp; &nbsp; <span style="color: #9F79EE;">&#40;</span>adder3<span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">,</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;.clk &nbsp; &nbsp; <span style="color: #9F79EE;">&#40;</span>clk<span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">,</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;.q &nbsp; &nbsp; &nbsp; <span style="color: #9F79EE;">&#40;</span>res_mul15<span style="color: #9F79EE;">&#41;</span><span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">;</span><br />
<br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">initial</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">forever</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp;<span style="color: #5D478B;">#</span><span style="color: #ff0055;">100</span><span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">if</span> <span style="color: #9F79EE;">&#40;</span><span style="color: #9932CC;">$time</span> <span style="color: #5D478B;">&gt;=</span> <span style="color: #ff0055;">1000</span><span style="color: #9F79EE;">&#41;</span> &nbsp;<span style="color: #9932CC;">$finish</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">end</span><br />
<br />
<span style="color: #A52A2A; font-weight: bold;">endmodule</span> <span style="color: #00008B; font-style: italic;">// test</span><br />
</div></div><p>
此时仿真报告中不再有 violation，仿真截图如下。</p><p>
由图可知，信号提前到达并保持不变的时间可达 8.6 ns，完全满足建立时间的时序要求。</p><p>
此种方法的根本原理，是将信号多次变化的时序，分散在多个周期内，来满足时序约束的要求。此外，流水线设计，并行设计等都可以优化时序。</p>
<p><img decoding="async" src="https://www.runoob.com/wp-content/uploads/2021/05/v-timing-check-3.png"></p>

<h3>$recovery, $removal</h3><p>
建立时间和保持时间的概念都是出现在同步电路的设计中。</p><p>
对于异步复位的触发器来说，异步复位信号也需要满足 recovery time（恢复时间）和 removal time（去除时间），才能有效的复位和释放复位，防止出现亚稳态。</p><p>

释放复位时，复位信号在时钟有效沿来临之前就需要提前一段时间恢复到非复位状态，这段时间为 recovery time。类似于同步时钟下触发器的 setup time。</p><p>
复位时，复位信号在时钟有效沿来临之后，还需要在一段时间内保持不变，这段时间为 removal time。类似于同步时钟下触发器的 hold time。</p><p>
recovery 与 removal time 示意图如下所示。</p>
<p><img decoding="async" src="https://www.runoob.com/wp-content/uploads/2021/05/v-timing-check-4.png"></p>
<p>系统任务 $recovery 与 $removal 分别用于 recovery 和 removal time 的检查，用法如下：</p>

<pre>$recovery (ref_event, data_event, recovery_limit) ;</pre><ul><li>
ref_event: 用于检查的参考信号，一般为清零或复位信号跳变沿；</li><li>
data_event: 被检查的信号，一般为时钟信号跳变沿。</li><li>
recovery_limit：设置的最小 recovery time。</li></ul>
<p>当 ref_event (reset) &lt; data_event (clock) 且 T(data_event - ref_event) &lt; recovery_limit 时，即复位信号在时钟信号到来之前如果不满足 recovery time，则报告中会打印 violation。</p>

<pre>$removal (ref_event, data_event, removal_limit) ;</pre><ul><li>
ref_event: 用于检查的参考信号，一般为清零或复位信号跳变沿；</li><li>
data_event: 被检查的信号，一般为时钟信号跳变沿。</li><li>
removal_limit：设置的最小 removal time。</li></ul>
<p>当 ref_event (reset) &gt; data_event (clock) 且 T(ref_event - data_event) &gt; removal_limit 时，即复位信号在时钟信号到来之后如果不满足 removal time，则报告中会打印 violation。</p>
<p>
Verilog 提供了同时检查 revomal 和 recovery 的系统任务：</p><pre>
$recrem (ref_event, data_event, recovery_limit, removal_limit);</pre>

<h3>$width, $period</h3><p>
有些数字设计，例如 flash 存储器，还需要对脉冲宽度或周期进行检查，为此 Verilog 分别提供了系统任务 $width 和 $period。用法如下：</p>

<pre>$width(ref_event, time_limit) ;</pre><ul><li>
ref_event: 边沿触发事件</li><li>
time_limit: 脉冲的最小宽度</li></ul>
<p>$width 用于检查边沿触发事件 ref_event 到下一个反向跳变沿之间的时间，常用于脉冲宽度的检查。如果两次相反跳边沿之间的时间小于 time_limit，则会报告 violation。</p>

<pre>$period(ref_event, time_limit) ;</pre><p>
$period 用于检查边沿触发事件 ref_event 到下一个同向跳变沿之间的时间，常用于时钟周期的检查。如果两次同向跳边沿之间的时间小于 time_limit，则报告中会打印 violation。</p>
<p><img decoding="async" src="https://www.runoob.com/wp-content/uploads/2021/05/v-timing-check-5.png"></p>
<p>检查信号 CLK 宽度和周期的 specify 块描述如下：</p>
<div class="example"><h2 class="example">实例</h2> <div class="example_code">
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">specify</span><br />
&nbsp; &nbsp; &nbsp; $width<span style="color: #9F79EE;">&#40;</span><span style="color: #A52A2A; font-weight: bold;">posedge</span> CLK<span style="color: #5D478B;">,</span> <span style="color: #ff0055;">10</span><span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">;</span> &nbsp;<br />
&nbsp; &nbsp; &nbsp; $period<span style="color: #9F79EE;">&#40;</span><span style="color: #A52A2A; font-weight: bold;">posedge</span> CLK<span style="color: #5D478B;">,</span> <span style="color: #ff0055;">20</span><span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">endspecify</span><br />
</div></div>
<h3>本章节源码下载</h3><p>
<a class="download" href="../wp-content/uploads/2021/05/v3.4_timing_check.zip">Download</a>   </p>				</div>
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	<a href="javascript:void(0);">Verilog 高级教程</a>	</div>
	
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	<li><a target="_top" data-id="23639" title="0.1 数字逻辑设计" href="../w3cnote/verilog2-tutorial.html" >0.1 数字逻辑设计</a></li>
	
		
	<li><a target="_top" data-id="23641" title="0.2 Verilog 编码风格" href="../w3cnote/verilog2-codestyle.html" >0.2 Verilog 编码风格</a></li>
	
		
	<li><a target="_top" data-id="23644" title="0.3 Verilog 代码规范" href="../w3cnote/verilog2-codeguide.html" >0.3 Verilog 代码规范</a></li>
	
		
	<li><a target="_top" data-id="23645" title="1.1 Verilog 门的类型" href="../w3cnote/verilog2-gate.html" >1.1 Verilog 门的类型</a></li>
	
		
	<li><a target="_top" data-id="23648" title="1.2 Verilog 开关级建模" href="../w3cnote/verilog2-level-modeling.html" >1.2 Verilog 开关级建模</a></li>
	
		
	<li><a target="_top" data-id="23656" title="1.3 Verilog 门延迟" href="../w3cnote/verilog2-gate-delay.html" >1.3 Verilog 门延迟</a></li>
	
		
	<li><a target="_top" data-id="23673" title="2.1 Verilog UDP 基础知识" href="../w3cnote/verilog2-udp.html" >2.1 Verilog UDP 基础知识</a></li>
	
		
	<li><a target="_top" data-id="23674" title="2.2 Verilog 组合逻辑 UDP" href="../w3cnote/verilog2-udp-logic.html" >2.2 Verilog 组合逻辑 UDP</a></li>
	
		
	<li><a target="_top" data-id="23677" title="2.3 Verilog 时序逻辑 UDP" href="../w3cnote/verilog2-udp-timing.html" >2.3 Verilog 时序逻辑 UDP</a></li>
	
		
	<li><a target="_top" data-id="23685" title="3.1 Verilog 延迟模型" href="../w3cnote/verilog2-delay-type.html" >3.1 Verilog 延迟模型</a></li>
	
		
	<li><a target="_top" data-id="23690" title="3.2 Verilog specify 块语句" href="../w3cnote/verilog2-specify.html" >3.2 Verilog specify 块语句</a></li>
	
		
	<li><a target="_top" data-id="23692" title="3.3 Verilog 建立时间和保持时间" href="../w3cnote/verilog2-setup-hold-time.html" >3.3 Verilog 建立时间和保持时间</a></li>
	
		<li>
	3.4 Verilog 时序检查	</li>
	
		
	<li><a target="_top" data-id="23708" title="3.5 Verilog 延迟反标注" href="../w3cnote/verilog2-sdf.html" >3.5 Verilog 延迟反标注</a></li>
	
		
	<li><a target="_top" data-id="23714" title="4.1 Verilog 同步与异步" href="../w3cnote/verilog-sync.html" >4.1 Verilog 同步与异步</a></li>
	
		
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	<li><a target="_top" data-id="23729" title="4.3 Verilog 跨时钟域传输：快到慢" href="../w3cnote/verilog2-fast2slow.html" >4.3 Verilog 跨时钟域传输：快到慢</a></li>
	
		
	<li><a target="_top" data-id="23731" title="4.4 Verilog FIFO 设计" href="../w3cnote/verilog2-fifo.html" >4.4 Verilog FIFO 设计</a></li>
	
		
	<li><a target="_top" data-id="23739" title="5.1 Verilog 复位简介" href="../w3cnote/verilog2-reset.html" >5.1 Verilog 复位简介</a></li>
	
		
	<li><a target="_top" data-id="23743" title="5.2 Verilog 时钟简介" href="../w3cnote/verilog2-clock.html" >5.2 Verilog 时钟简介</a></li>
	
		
	<li><a target="_top" data-id="23757" title="5.3 Verilog 时钟分频" href="../w3cnote/verilog2-clock-division.html" >5.3 Verilog 时钟分频</a></li>
	
		
	<li><a target="_top" data-id="23768" title="5.4 Verilog 时钟切换" href="../w3cnote/verilog2-clock-switch.html" >5.4 Verilog 时钟切换</a></li>
	
		
	<li><a target="_top" data-id="23779" title="6.1 Verilog 低功耗简介" href="../w3cnote/verilog2-low-power.html" >6.1 Verilog 低功耗简介</a></li>
	
		
	<li><a target="_top" data-id="23788" title="6.2 Verilog 系统级低功耗设计" href="../w3cnote/verilog2-lower-power-design.html" >6.2 Verilog 系统级低功耗设计</a></li>
	
		
	<li><a target="_top" data-id="23792" title="6.3 Verilog  RTL 级低功耗设计（上）" href="../w3cnote/verilog2-rtl-low-power-design-1.html" >6.3 Verilog  RTL 级低功耗设计（上）</a></li>
	
		
	<li><a target="_top" data-id="23796" title="6.4 Verilog RTL 级低功耗设计（下）" href="../w3cnote/verilog2-rtl-low-power-design-2.html" >6.4 Verilog RTL 级低功耗设计（下）</a></li>
	
		
	<li><a target="_top" data-id="23806" title="7.1 Verilog 显示任务" href="../w3cnote/verilog2-display.html" >7.1 Verilog 显示任务</a></li>
	
		
	<li><a target="_top" data-id="23813" title="7.2 Verilog 文件操作" href="../w3cnote/verilog2-file.html" >7.2 Verilog 文件操作</a></li>
	
		
	<li><a target="_top" data-id="23825" title="7.3 Verilog 随机数及概率分布" href="../w3cnote/verilog2-random.html" >7.3 Verilog 随机数及概率分布</a></li>
	
		
	<li><a target="_top" data-id="23847" title="7.4 Verilog 实数整数转换" href="../w3cnote/verilog2-real2int.html" >7.4 Verilog 实数整数转换</a></li>
	
		
	<li><a target="_top" data-id="23851" title="7.5 Verilog 其他系统任务" href="../w3cnote/verilog2-other-task.html" >7.5 Verilog 其他系统任务</a></li>
	
		
	<li><a target="_top" data-id="23862" title="8.1 Verilog  PLI 简介" href="../w3cnote/verilog2-pli-intro.html" >8.1 Verilog  PLI 简介</a></li>
	
		
	<li><a target="_top" data-id="23865" title="8.2 Verilog TF 子程序" href="../w3cnote/verilog2-tf.html" >8.2 Verilog TF 子程序</a></li>
	
		
	<li><a target="_top" data-id="23869" title="8.3 Verilog TF 子程序列表" href="../w3cnote/verilog2-tf-sub.html" >8.3 Verilog TF 子程序列表</a></li>
	
		
	<li><a target="_top" data-id="23870" title="8.4 Verilog ACC 子程序" href="../w3cnote/verilog2-acc.html" >8.4 Verilog ACC 子程序</a></li>
	
		
	<li><a target="_top" data-id="23872" title="8.5 Verilog ACC 子程序列表" href="../w3cnote/verilog2-acc-sub.html" >8.5 Verilog ACC 子程序列表</a></li>
	
		
	<li><a target="_top" data-id="23876" title="9.1 Verilog 逻辑综合" href="../w3cnote/verilog2-logic-sumarry.html" >9.1 Verilog 逻辑综合</a></li>
	
		
	<li><a target="_top" data-id="23882" title="9.2 Verilog 可综合性设计" href="../w3cnote/verilog2-integrated-design.html" >9.2 Verilog 可综合性设计</a></li>
	
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